1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to an improvement of a programming high-voltage pulse generator in a 5 V-only electrically erasable programmable read-only memory (EEPROM).
2. Description of the Prior Art
FIG. 1 is a schematic diagram showing a structure of a conventional programming high-voltage generating circuit, as disclosed in "High-Voltage Regulation and Process Considerations for High-Density 5 V-only E.sup.2 PROM's" by Duane H. Oto et al., IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5 (1983), pp. 532-538. Referring to FIG. 1, the structure and the operation of the conventional circuit for generating a programming high-voltage pulse V.sub.pp will be described in the following.
This circuit comprises as a reference signal generating system: a reference voltage generator 1 for generating a reference voltage signal V.sub.ref for controlling the height of a programming high-voltage pulse V.sub.pp and supplying the reference voltage signal V.sub.ref to an RC network 5; an oscillator 2 for supplying two kinds of clock pulses not overlapping with each other to the respective gate electrodes of the MOS transistors 9 and 10 included in the RC network 5 so that the time constant of the RC network 5 is controlled; the RC network 5 for making gentle the rise of the reference voltage signal V.sub.ref from the reference voltage generator 1 in response to the clock signal frequency from the oscillator 2 and providing the signal V.sub.ref to a node A; a timer 3 for generating a pulse signal for controlling the pulse width of the high-voltage pulse V.sub.pp ; and a MOS transistor 4 turning on and off in response to the signal from the timer 3 so as to control the potential at the node A. The above-stated RC network 5 comprises a switched-capacitor 6 and a capacitor 7. The switched capacitor 6 comprises MOS transistors 9 and 10 turning on and off alternately by receiving at the gate electrodes thereof the two phase nonoverlapping clock signals from the oscillator 2 and also comprises a capacitor 11 having one electrode connected to a junction of the MOS transistors 9 and 10 and the other electrode grounded. The capacitor 7 has one electrode connected to an output terminal of switched-capacitor 6 and to the node A and the other electrode thereof is grounded. The capacitor 7 and the capacitor 11 both are formed of an oxide film formed by the same manufacturing process as for a gate oxide film of a MOS transistor on the same chip. One end of the MOS transistor 4 is connected to the node A and the other end thereof is grounded.
Further, the circuit shown in FIG. 1 comprises as a signal amplifying system: a comparator 12 for receiving and comparing the potential at the node A and a signal from a voltage divider 14 to provide an activation signal to a driver 15 if the potential at the node A is higher than the signal level from the voltage divider 14; a charge pump 13 responsive to the signal from the driver 15 to multiply the voltage so as to provide a programming high-voltage pulse V.sub.pp to a memory transistor (not shown) of the EEPROM and to the voltage divider 14; and the voltage divider 14 for dividing the voltage signal received from the charge pump 13 by a predetermined division ratio and providing the result of the division to the comparator 12.
FIG. 2 is a diagram showing a waveform of the programming high-voltage pulse V.sub.pp. The height h of the pulse V.sub.pp is controlled by the signal from the reference voltage generator 1, a delay time (a rise time constant) .tau. is controlled by the RC network 5; and a pulse width w is controlled by a signal from the timer 3. Now, referring to FIGS. 1 and 2, the operation of the programming high-voltage generator will be described.
When the output signal from the timer 3 falls to the level "L", the MOS transistor 4 is brought into the OFF-state. As a result, the reference voltage signal V.sub.ref from the reference voltage generator circuit 1 is transmitted to the node A through the RC network 5. The RC network 5 comprises the switched-capacitor 6 and the capacitor 7 and in response to the signal from the oscillator 2, the MOS transistors 9 and 10 are turned on and off alternately so that electric charges from the reference voltage generator 1 are successively transferred. The time constant .tau. thereof is controlled by the signal from the oscillator 2 and the ratio of the capacitance 7 and 11. The potential at the node A serves as an input of the comparator 12, where it is compared with the output voltage V.sub.pp from the charge pump 13 divided by the voltage divider 14. The output signal of the comparator 12 is supplied to the driver 15 for driving the charge pump 13. The comparator 12 generates a signal for activating the driver 15 when the potential at the node A is higher than the voltage signal level from the voltage divider 14. Accordingly, the voltage obtained by dividing the voltage of the node A by a division ratio of the voltage divider 14 becomes the output signal of the charge pump 13, that is, the programming high-voltage pulse V.sub.pp. Thus, by the above described operation, the programming high-voltage pulse is generated.
Then, when the output signal from the timer 3 attains the level "H", the MOS transistor 4 is brought into the ON-state and the potential at the node A becomes a ground potential through the MOS transistor 4. As a result, an activation signal is not generated from the comparator 12 and the generation of the programming high-voltage pulse V.sub.pp from the charge pump 13 is stopped.
The potential at the node A rises to the level of the reference voltage signal V.sub.ref with the time constant .tau. of the RC network 5 in response to the turn-off of the MOS transistor 4. Accordingly, the output pulse V.sub.pp from the charge pump 13 rises also with the time constant .tau. . The rise of the pulse signal V.sub.pp is made gentle by using the RC network 5 so that too high an electric field may not be applied to the tunnel oxide film of the memory transistor of the EEPROM. In the conventional device, the rise time constant .tau. is set to 600 microseconds.
FIG. 3 is a sectional view showing schematically a structure of a memory transistor of an EEPROM. In FIG. 3, the memory transistor comprises: a drain 18 and a source 19 formed on the surface of a semiconductor substrate 20; a floating gate 17 formed on the drain 18 through a tunnel oxide film 21 to store a signal charge; and a control gate 16 formed on the floating gate 17 through an interlayer oxide film 23 to control the storage and the emission of a signal charge in the floating gate 17. The control gate 16 and the floating gate 17 both are normally formed of polysilicon. Therefore, the interlayer oxide film 23 is hereinafter referred to as the polysilicon-polysilicon interlayer oxide film 23 for convenience' sake. Now, the programming operation of the memory transistor will be described. The programming operation comprises an erasing mode and a writing mode. First, the operation in the erasing mode will be described.
In the erasing mode, the high-voltage pulse V.sub.pp from the programming high-voltage pulse generator (see FIG. 1) is supplied to the control gate 16, and the source 19, the drain 18 and the substrate 20 are grounded. More specifically, in FIG. 3, the equations V.sub.g =V.sub.pp and V.sub.D =V.sub.S =0 are established. Under this condition, a high electric field is applied to the tunnel oxide film 21. In consequence, a tunnel current flows between the drain 18 and the floating gate 17 through the tunnel oxide film 21 and electrons are injected into the floating gate 17, so that the threshold voltage of the memory transistor is increased. In other words, the erasing mode means a mode in which electrons are injected into the floating gate.
In the writing mode, the high-voltage pulse V.sub.pp from the high-voltage pulse generator is applied to the drain 18 (V.sub.D =V.sub.pp), so that the source 19 is brought into an electrically floating state and the control gate 16 and the semiconductor substrate 20 are grounded (V.sub.g =0). In this condition, electrons flow out of the floating gate 17 through the tunnel oxide film 21 so that positive charges are stored in the floating gate 17. As a result, the threshold voltage of the memory transistor is lowered.
The electric field applied to the tunnel oxide film 21 for defining a shift amount of the threshold voltage (that is, an amount of electrons flowing in and out of the floating gate 17) is determined by a ratio of a capacitance between the control gate 16 and the floating gate 17 and a capacitance between the floating gate 17 and the drain 18. When the thickness of the polysilicon-polysilicon interlayer oxide film 23 and the thickness of the tunnel oxide film 21 are varied, the electric filed applied to the tunnel oxide film 21 varies even if the same voltage is applied to the control gate 16 at the time of programming. Therefore, even if the same programming high-voltage pulse V.sub.pp is applied to the control gate 16 in the erasing mode, the shift amount .DELTA.Vth of the threshold voltage of the memory transistor changes in case where the thicknesses of these oxide films are varied. In the following, referring to the figures, a relation between the shift amount .DELTA.Vth of the threshold voltage and the thicknesses of the oxide films will be specifically described. Although the following description concerns only the erasing mode for convenience' sake, it is the same with the writing mode.
FIG. 4 is a graph showing a threshold voltage shift amount .DELTA.Vth obtained by computer simulation in case where the thickness of the tunnel oxide film is changed in a range of 80 .ANG. to 100 .ANG. with the thickness of the polysilicon-polysilicon interlayer oxide film being 800 .ANG.. In FIG. 4, the horizontal axis represents a pulse width of the pulse V.sub.pp and the vertical axis represents a threshold voltage shift amount .DELTA.Vth. The potential of the pulse V.sub.pp applied to the control gate is set to be 21 V and the rise time constant .tau. thereof is 0.6 millisecond. As seen from FIG. 4, in the case of the pulse V.sub.pp with a pulse width of 2 milliseconds, the threshold voltage shift amount .DELTA.Vth largely changes in a range of 1.9 V to 4.5 V according to the thickness of the tunnel oxide film.
FIG. 5 is a graph showing a threshold voltage shift amount .DELTA.Vth obtained by computer simulation in case where the thickness of the polysilicon-polysilicon interlayer oxide film is changed in a range of 700 .ANG. to 900 .ANG. with the thickness of the tunnel oxide film being maintained 90 .ANG.. In FIG. 5, the horizontal axis represents a pulse width of the pulse V.sub.pp and the vertical axis represents a threshold voltage shift amount .DELTA.Vth. The voltage of the pulse V.sub.pp applied to the control gate is 24 V and the rise time constant .tau. thereof is 1 millisecond. As seen from FIG. 5, the threshold voltage shift amount .DELTA.Vth largely changes as the thickness of the polysilicon-polysilicon interlayer oxide film changes.
Therefore, if the thicknesses of the oxide films are varied, it is necessary to change the waveform of the pulse V.sub.pp according to the thicknesses of the oxide films so as to obtain a constant threshold voltage shift amount .DELTA.Vth. This is because the shift of the threshold voltage is caused by the flowing-in and flowing-out of electric charges to/from the floating gate and the flowing-in and flowing-out amount of electric charges is defined by the electric field accross the tunnel oxide and therefore by the waveform of the high-voltage pulse V.sub.pp. It is important to make the threshold voltage shift amount .DELTA.Vth constant for the purpose of securing the reliability of the EEPROM and a stable operation for reading and storing data.
In a conventional method, as described in the above cited prior art document, control is made by a program to change the level of the output signal V.sub.ref of the reference voltage generating circuit for each chip according to the thicknesses of the oxide films. However, the above described conventional method involves problems that the time required for a function test of an EEPROM is long and a programming circuit needs to be provided for each chip.